As the performance and data throughput requirements for networking and computing applications increase, the performance and data throughput requirements for many of the required individual subsystems also increase. Transferring data between the main memory and the system processor, for example, is often a significant performance bottleneck in any computing system. Even the fastest standard Dynamic Random Access Memory (DRAM) cannot keep up with the ever increasing bus speeds used on many computing systems.
Synchronous Dynamic RAM (SDRAM) is a type of DRAM that demonstrates improved performance and data throughput. While DRAM has an asynchronous interface (i.e., it immediately reacts to changes in its control inputs), SDRAM has a synchronous interface (i.e., it waits for a clock pulse before responding to its control inputs). Likewise, Double Data Rate (DDR) SDRAM is a further evolution of SDRAM that is used in many computing systems. As originally proposed, SDRAM acts on only the rising edge of the clock signal (i.e., each low-to-high transition). DDR SDRAM, on the other hand, acts on both the rising and falling edges, thereby potentially increasing the data rate by a factor of two. Further performance improvements are obtained in DDR-2 (2×) and QDR-2 (4×) by phase shifting the clock signal to obtain additional rising and falling edges.
SDRAM enjoys wide spread application in both low-end consumer computing applications, as well as in high end networking switches and routers. Currently, the data throughput (i.e., the speed) of SDRAM is limited by a delay skew spread of the parallel bus that carries the parallel data that is being read from or written to the memory. Generally, in the presence of a delay skew spread, the rising and falling edges of the data signals on the parallel bus are not aligned. The skew spread is often attributed to variations in process, voltage, temperature or aging (PVTA).
A need therefore exists for methods and apparatus for monitoring and compensating for skew on high speed parallel buses in SDRAM and other ASIC devices. A further need exists for a microprocessor-based I/O skew controlling technique.